1. Field of the Invention
This invention relates to integrated circuit technology in general, and more particularly, to circuits that generate reference voltages in said integrated circuit technology.
2. Prior Art
The rapid improvements in the development and use of the CMOS technology has created a need for a process friendly reference voltage generating system. As is used in this application, process friendly means using the regular or standard CMOS process to generate a desired circuit component, module or system. In particular, a process friendly reference voltage generating system is realized from use of a regular or conventional CMOS process.
The generation of a reference voltage using modified CMOS processes has been done in the prior art. Known prior art implementations use two FETs with different threshold voltages. The prior art also teaches that the device threshold voltages can be controlled by ion implementation and/or varying the geometries of the devices. The examples of the prior art teachings are set forth in U.S. Pat. Nos. 4,305,011; 4,442,398; 4,464,588; 4,100,437; 4,327,320; 4,472,871; 4,453,094 and 4,742,292.
Even though the prior art teachings are a step in the right direction in that they suggest using, to the extent possible, a single process for providing the reference voltage generation, they fall short of intended goals in that none uses the standard or conventional CMOS process to provide a reference voltage generation. Stated another way, additional process steps, not common to the standard CMOS process, or devices not commonly used in CMOS technology, are required to generate the prior art reference voltage generators. The additional process steps and devices increase product cost.